Completed Design

Completed Design. Means that a particular circuit or chip design has been completed, which occurs when the design is taped-out resulting in the generation of a GDSII file, and in the design process the design has been compiled and transformed using Amplify ASIC RC from RTL format (Verilog or VHDL) to a structural logic netlist (Verilog, VHDL or EDIF) with fully placed logic gates for physical implementation.